Signal newsletter · Issue #4
Google's TPUs leave Google Cloud
Hello again, and welcome to issue #4! 👋
This week Google’s custom AI chips escaped Google Cloud, NVIDIA shipped production CUDA for its next GPU architecture, and an IPO filing showed how seriously the big labs are hedging their silicon. Five minutes, tops. Let’s go.
📡 The Big Signal: Google’s TPUs land on a rival cloud
In short: for the first time, you’ll be able to rent Google’s AI chips on a hyperscale cloud that isn’t Google’s.
At Oracle AI World on Tuesday (27 October), Oracle and Google said Google’s Tensor Processing Units will be available on Oracle Cloud Infrastructure starting in calendar 2027, with capacity ramping over several years — the first time TPUs land on a hyperscaler that isn't Google. Oracle supplies power, cooling and networking; Google supplies the chips and software.
The eighth-generation lineup splits the work: TPU 8t for training and TPU 8i for inference and agent-style jobs. Google also pointed builders at TorchTPU, its open-source PyTorch stack for TPUs. Pricing, first regions and year-one capacity were not disclosed.
Why this matters: AI shops no longer need Google Cloud just to get Google silicon, and buyers gain another lever when NVIDIA capacity is tight or pricey.
Sources: Oracle ·
⚡ Quick Hits
In short: NVIDIA’s next GPU architecture is now ready for production CUDA apps.
CUDA 13.5 makes Vera Rubin generally available.
The toolkit moves Vera Rubin support from early access to GA, adds Multi-Process Service v3 for smarter GPU sharing, multi-GPU CUDA Tile communication, and a public preview of the Nsight Perf SDK for AI for always-on profiling of long runs.
Why this matters: if your stack targets Rubin, you can stop treating the new chips as a science project and start shipping against them.
In short: Anthropic’s IPO papers show it runs Claude across four chip families as one pool.
Anthropic hedges Nvidia with four chip brands.
In its S-1 (amended 2 November), Anthropic says it manages compute “as a single, fungible pool” across AWS Trainium, Google TPUs, NVIDIA GPUs and AMD GPUs, routing each job to the most productive chip. Building that layer took years, it says. The filing also commits at least $114.5 billion of Google TPU spend between April 2026 and July 2033.
· Fortune
Why this matters: the biggest AI labs are writing software to swap chips the way they swap cloud regions, which weakens any single vendor’s pricing power over time.
In short: ST rebuilt its edge-AI toolbox so STM32 teams can pick, tune and test models in one place.
ST Edge AI Suite gets four new tools.
Model Explorer browses ST’s 400-plus pre-trained models, Dataset Factory turns raw sensor data into training sets, Model Factory handles customisation and quantisation for STM32 MCUs, and Model Bench benchmarks models on real boards in ST’s remote farm. The new tools are due late November.
Why this matters: shipping AI on a tiny microcontroller gets less of a scavenger hunt and more of a normal engineering workflow.
In short: Altera’s next FPGA family aims at AI infrastructure and the edge, with silicon later.
Altera unveils Agilex 2X.
The portfolio spans four families; Agilex 27 launches first with a claimed 1.8× performance-per-watt lift and a chip-wide HyperFlow network-on-chip. Quartus support for early-access customers starts mid-November; engineering samples are expected in the second half of 2027.
Why this matters: FPGAs still win for custom data paths next to sensors or networks, and this roadmap keeps that option alive beside GPUs and TPUs.
🛠️ Tool of the Week: QuartusIQ
In short: an AI companion inside Altera’s FPGA tools that knows your project and helps close timing.
QuartusIQ sits in Quartus Prime Pro and talks to you in plain English about the design you have open: device, IP, constraints, reports and timing. Through a Model Context Protocol interface it can drive multi-step compile, verify and timing workflows while you keep the final call. Altera claims up to 1.5× faster design cycles. It ships with Quartus Prime Pro v26.3 (from 28 October) and can run on-premises on NVIDIA DGX Station for Windows if your IP must not leave the building.
Why this matters: FPGA timing closure eats months; an agent that already sees your reports beats a chatbot that needs you to paste logs.
💡 One Takeaway
Build for chip choice, not chip loyalty.
This week Google put TPUs on Oracle, Anthropic described a four-vendor compute pool, and CUDA 13.5 locked in the next NVIDIA generation. The durable skill is keeping training and serving stacks portable enough that a better price or a freer queue elsewhere is a config change, not a six-month rewrite. If your code only runs on one accelerator brand, that brand sets your bill.
That’s issue #4! What did you make of it? Just hit reply: we read every message, and we’d love to know what you want more (or less) of.
And if Signal Tech saved you some scrolling this week, forward it to a friend who’d enjoy it. That’s how we grow.
Until next Friday,
The Signal Tech team 📡
The tech that matters, minus the noise.
First sent by email on Friday, 6 November 2026. View this issue on beehiiv.